The timing diagram represents the clock cycle and duration, delay, content of address bus and data bus, type of operation ie.
Similar Mind Maps
The first byte of an instruction is the opcode. An instruction may be more than one byte long. the other bytes are data or operand address.
the program counter keeps the addressof the next instruction to executed.
in the beginning of the fetch cyclewhere opcode is available is send to the memory.
the memory place the opcode on the data bus , so as to transfer it to CPU.
the entire operation of fetching an opcode takesthree clock cycles.. A slow memory make take more time
the clock cycle for which the CPU waits is called wait cycle. most the CPU have been designed to introduced wait cycle to cope with slow memories.
The opcode fetched from the memorygoes to the data register (Dr) and the theInstruction register ( Ir)
from the instruction register it goes to the decoder circuitry which decodes the instruction. the decodorcircuitry is within the micro processsor.
Soon after the instruction isdecoded execution begins. If theoperand is in the general purpose register execution is immediately performed.
the time taken in decoding and executionis one clock cycle.
Suppose if the data or operand are still in the memory. The CPU has to performsome read operation to get the desired data.
after receving the data it perform execution.the read cycle is similar to the fetch cycle
In case of a read cycle , the quantity receivedare in the form of data or operand instead of an opcode.
In some operation write cycle is performed.In the write cycle date is sent from the CPU to memory.
Thus we see that an execute cycle consist of an read or write cycle
An instruction is a command givento the computer to perform a specified operation on a given data
The CPU fetches the instruction stored at memory and executes it one by one.To produce the final result.
the necessary steps that an CPU takes to fetch data and instruction from the memory and executes constitute an instruction cycle.
We come to the point that theinstruction cycle consist of a fetch and execute cycle.
in the fetch cycle the CPU fetches anopcode from the memory and the steps to fetch an opcode constitute a fetch cycle.
the necessary steps which arecarried out to get data from the memory and perform the operationspecified in the instruction constitute anexecute cycle.
the necessary steps carried out to performfetch, a read or write operation constitute amachine cycle.
An instruction consist of several machine cycle
The opcode of an instructionis fetched in the first machine cycleof an instruction cycle
Most of the single byte instruction requires onlyone machine cycle to fetch the opcode and execute the instruction
Two byte and three byte instruction requiremore than one machine cycle.
additional m/c cycle are required to read or write data into memory orI/o devices.
Memory mapped I/O
In memory mapped i/o there is onlyone address space.
Address space is defined as the set of all addresses that a micro processor can generate.
some address is assingned to the memories while some to i/odevices.
I/O devices is also termedas the memory location and one address is assigned to it
The address for I/O devices are differentfrom the address which have been assigned to memories.
the memory address which have not been assigned to memories can be assigned to I/O device.
For eg 2500, 2501, 2502,
In this scheme all the data transferinstruction of the microprocessorcan be used for memory as well as I/O devices
I/O mapped I/O scheme
in this scheme the address assiged to the memory locationcan also be assigned to the I/O devices.
In other word same addressmay be assigned
the microprocessor must issue a signal to distinguish whether the address on the address bus for memory or an I/o device.
the intel 8085 issues an IO/m signalfor this purpose
When the signal is high on the address bus , it is for I/O devices.
When the address is low then it is for memory location
IN and OUT instruction are used for I?O devices
IN instruction is used to read the dataof an input device while the OUT instructionis used to send data to output devices
The interupt of 8085
The Intel 8085 has five interupts namelyTRAP,RST 7.5, RST 6.5, RST 5.5 and INTR.
the TRAP has the highest priority whilethe INTR has the lowest.
When interprets are used they areenabled by the software using the instruction EI (enable interupt) in themain program
The instruction EI enables all theinterupts while the instruction DIis used to disable interupts
In certain situation it may bedesired to prevent the occurence of interupts while a particular task is being performed by the microprocessor. This can be done with the help of DI instruction.
The DI instruction resets the interupt enableflipflop and disable all the interupts exceptnon-maskable interupt TRAP.
When the interupt goes high the processor complets it current instruction and saves theprogram counter on stack.
It also resets the interupt enableflip flop before taking up ISS so thatthe occurence of further interupts is prevented before execution of ISS.