External Interrupt

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External Interrupt
Configure the GPIO as Input (GPIO LEVEL)
REMEMBER ALWAYS HAVE EALLOW & EDIS
GPA/B/C UD = 0 ENABLE RESISTOR PULL UP TO VCC
EALLOW;
GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull up
GP A/B/C MUX 1/2 = 00 FOR IN_OUT
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0;
GP A/B/C DIR = 1 FOR OUTPUT
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0; // GPIO50 is Input
GP A/B/C CTRL // FOR TIME OF THE SAMPLE
GpioCtrlRegs.GPBCTRL.bit.QUALPRD2 = 0xFF; // For value GPIO50
GP A/B/C QSEL = 00 FOR SYNC WITH SYSCLK
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Input is sync with SYSCLK
EDIS;
See the Figure 4_4 for GPIO Multiplexing Diagram in 69'th page
Configure External Interrupt MUX (EXTERNAL MUX LEVEL)
XINTxCR (x = 3 .. 7) CONFIURE KIND OF INTERRUPT WILL APPEAR
POLARITY ( CHOICE EDGE)
10 FALLING EDGE
11 BOTH RISING EDGE AND FALLING
XIntruptRegs.XINT3CR.bit.POLARITY = 3; // Both Falling and Risibg edge interrupt
00 FALLING EDGE (ACTIVE)
XIntruptRegs.XINT3CR.bit.POLARITY = 0; // Falling edge interrupt
01 RISING EDGE (ACTIVE)
XIntruptRegs.XINT3CR.bit.POLARITY = 1; // Rising edge interrupt
Choice one
ENABLE EXTERNAL INTERRUPT
0 IS DISABLE
1 ENABLE
XIntruptRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT3
GPIOXINTxSEL (x = 3..7) ASSIGNT GPIO PIN IS EXTERNAL INTERRUPT FROM XINT3 TO XINT7
Remember always have EALLOW & EDIS
Only one source interrupt for XINTx
GPIOSEL = 00000 TO 11111 FOR GPIO32 TO GPIO63
EALLOW;
GpioIntRegs.GPIOXINT3SEL.bit.GPIOSEL = 18; // Choice GPIO50 for Xint3
EDIS;
See the Figure 6_4 PIE Sources and External Interrupt in128'th page
Configure PIE interrupt (PIE LEVEL)
PIEIFRx (x = 1 .. 12) (PIE Interrupt Flag Register from group 1 to 12) don't care this register
Automatic set when has interrupt, and automatic clear when fetch to interrupt vector
PIECTRL (PIE CONTROL REGISTER)
PIEVECT indicate the address within the PIE vector table
REMEMBER ALWAYS HAVE EALLOW & EDIS
EALLOW;
PieVectTable.XINT3 = &xint3_isr;
EDIS;
ENPIE
0 IS DISABLE
1 IS ENABLE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PIEIERx (x = 1 .. 12) PIE Interrupt Enable Register form group 1 to 12
INTx.y (y form 1 to 8) = 0 : disable an interrupt within a group
INTx.y (y form 1 to 8) = 1 : enable an interrupt within a group
PieCtrlRegs.PIEIER12.bit.INTx1= 1; // Enable Xint3 in the PIE: Group 12 interrupt 1
PIEACK (ACKNOWLEDGE REGISTER)
Bit 0 to 11 is PIEACK group 1 to 12
Put at the end of Interrupt Routine for making enable of another interrupt
interrupt void xint1_isr(void)
{
...
...
PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; // Acknowledge this interrupt to get more from group 12
}
Configure CPU LEVEL
DBGIER (Debug Interrupt Enable Register) don't care because use in Real_time
IFR (Interrupt Flag Register)
Should clear all Interrupt Flag at the begin program
// Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt Service Routines (ISR).
// This will populate the entire table, even if the interrupt is not used in this example.
// This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
IER (Interrupt Enable Register) 14 bit for INT1 .. INT14, 2 bit for RTOSINT, DLOGINT
INTx = 0 : Disable CPU INTx level (x = 1 .. 14)
INTx = 1 : Enable CPU INTx level (x = 1 .. 14)
IER |= M_INT12
CAN ENABLE FOR 12 INTERRPUT SOURCE TO CPU BECAUSE USE OR STRUCE |=
INTM (Global Enable)
= 1 Disable
= 0 Enable = EINT command (because define ENIT= CLRC INTM)
EINT; //#define EINT asm(" clrc INTM")
XINT3 from Group 12 and the address is INTx1
Must see Table 6_4 PIE MUXed Peripheral